Notes

1. The original LSI-11 processor was a quad card that included 8Kb of memory and five 40 pin sockets. Four were for the base processor (data, control and two microcode chips) and one for the KEV11 option which added extra microcode for the EIS and FIS instructions. It was possible to code your own microcode routines using the KEV11 option socket. Internally, the chip set only used 8 bit data paths.

   The later LSI-11/2 processor used the same chip set, but had a dual width card and no onboard memory. Unlike most other PDP-11's (except the T11 chip), the processor status word had to be accessed with special instructions and was not addressable at 0177776.

2. The PDP11/05 and /10 had the unique ability to run programs in the CPU registers (address 0177700-0177706). The microcode even incremented the PC by one instead of two!

3. The original PDP-11/20 documentation referred to a strip down version called the PDP11/10. This was latter renumbered to PDP11/15, and the PDP11/10 became the OEM version of the PDP11/05. The PDP-11/20 was the only machine to use random logic instead of microsequencing for the processor.

4. This is the original model PDP11 and the only one to use state login instead of microcode. There was a "Digital Special Systems" option called the KS-11 that added extended memory addressing and user protection modes. I could find no documentation for this option. Apparently it allowed user mode access to the I/O page registers of the EAE as a special case! (images)

5. The original version had only 18 bit of addressing even though the chip set implemented a full 22 bits. The processor was expandable by adding additional chips. The basic data and control chips were mounted on a single 40 pin chip carrier. The MMU was added as a second chip, and the FPU as a third. The final option was a CIS instruction set.

   The latter PDP11/23+ used a quad width board that added two serial ports, extensive bootstrap/diagnostic ROM and programmable line frequency clock.

6. This evolved into three versions (/34,/34a,/34c). It was a a 2 hex board processor, with a optional third quad card to run a seven segment display and keypad console (which used an Intel 8008). A bit slice floating point processor was designed using sixteen 2901's (for a 64 bit data path), and the CPU was upgraded to the /34a to show that it was compatible with the FPU. A latter mid-life upgrade was a cache, which resulted in the /34c. Ironically, the CPU clock was slowed to accommodate the cache timing.

7. The CPU had several options to add EIS, FIS and a MMU. These cards added extra microcode, holding registers, data multiplexers and shift logic. Adding these options was a nightmare as dozens of jumpers had to be changed on the CPU modules.

8. The FPU is implemented using 2901's (as was the 11/34). If the cache module failed, it was possible to remove the card and have the CPU function normally, but rather more slowly!

9. The PDP11/45/50/55 were basically the same family of machines. The MMU and FPU were optional. Generally the /45 had core memory only, the /50 had additional MOS fastbus memory and the /55 had bipolar fastbus memory. There was a redesigned of the FPU and a flash new (white) front panel for the number crunching PDP11/55. Several OEM manufacturers offered cache boards that ran on the fastbus.

10. Released after the PDP11/73 as a cheaper version without cache support.

11. Featured the new 'corporate cabinet', a pokey front panel and room to fit two RK05 or RK06 (latter RK07) disk drives. The first machine to feature ECC MOS memory as standard (latter the 11/44). The FPU was standard in microcode, with a real FPP as an option. A user writable control store was also available. First unibus machine to use tristate logic internally for speed and to save data multiplexers.

12. This was the upgrade for the PDP11/45. It shared a lot of the design used in the 11/45, but the fastbus was replaced with a 32 bit wide massbus, a 2Kb cache, a separate memory bus and 22 bit addressing for 4Mb of memory. A separate cabinet was added to accommodate the memory.

    The Unibus on this machine was a disaster and had a bandwidth of only 1Mbyte/sec compared to about 1.7 for other machines. There were extra delays of 100ns for the unibus map and 240ns for the cache cycle.

13. First machine to use the J11 'PDP-11/70 on a chip', fabricated by Harris Semiconductor.

14. Memory used PMI (Private Memory Interconnect)

15. Memory is on the processor card (and not expandable) in either 2Mb or 4Mb (70ns parts).

16. There are some obscure instructions used on some processors :-

    Mnemonic	Description	Processor
    CSM	Call Supervisor Mode	/44/53/73/83/84/93/94
    LDUB	Load microbreak register	/60
    MED	Maintenance Instruction	/60
    MFPS	Move from processor status	/03/21/23/24/34/44/53/60/73/83/84/93/94
    MFPT	Move from processor type	/23/24/44/53/73/83/84/93/94
    MTPS	Move to processor status	/03/21/23/24/34/44/53/60/73/83/84/93/94
    SPL	Set Priority Level	/44/45/50/53/55/70/73/83/84/93/94
    TSTSET	Test destination, unlock	/53/73/83/84/93/94 (J11 chip)
    WRTLCK	Write lock contents of R0	/53/73/83/84/93/94 (J11 chip)
    XFC	Extented Function Code	/60 (user microcode option)