PDP11 Quirks

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• The PDP11/05/10 could execute a program out of the registers at memory locations 0177700-0177706. The program counter would only increment by one instead of two, and odd PC values were allowed. Branch instructions still went two locations per offset count. (example)

• The PDP11/20 did not timeout bus requests, so it was possible to completely hang the processor if you requested an interrupt and withdraw it before it was granted. Latter PDP11 processors would timeout all requests (about 15us). Latter bus terminator cards would detect bus and NPR grants and assert SLAVE SYNC to speed up the timeout procedure. Normally no grants should reach the end of the bus.

• The cache option on a PDP11/34 required the processor speed to be decreased.

• The PDP11/35/40 had an odd definition for the run light on the console panel. Normally it means that the processor is running a program. The run light on a PDP11/35/40 showed when the processor clock was running and not stopped for a bus transaction. It had a separate console light to show that the processor was halted and in console mode. (light chaser program)

• The PDP11/44 had a late field change order to correct a fault with the PIR (program interrupt request register). Apparently, the only software that seriously used it was the MERT from Bell Labs. This machine was the only separate instruction / data space machine not to have a dual register set. Apparently, the early microcode was riddled with bugs.

• The PDP11/45/50/55 had separate register deposit and examine switches rather than using the normal switches and addresses 0777700-0777707. They were the only PDP11 to have two unibuses (only if fastbus memory was present) which were normally jumpered together.

• The PDP11/70 had the slowest unibus due to interactions with the unibus mapping hardware and cache controller.

• The PDP11/70 preserved the lamp test switch (hidden between data switch 0 and load address) even though it had LEDs instead of incandescent lamps.

• The original PDP11/73 (KFJ11-AA) had flaky sockets for the gate array chips which produced random CPU failures.

• The PDP11/45/50/55/70 have a programmable data register (selectable by a front panel switch). It was fun to program light chasers in the kernel idle loop. The PDP11/60 was also programmable, but it's a bit boring using seven segment displays.

• The T11 microprocessor chip (used in the SBC11/21 and RQDX1/2 controllers) could be configured to use either a 8 bit or 16 bit data bus.