Production PDP-11 Models
The first of the LSI-11 series, it also introduced a new (cheaper)
bus call the Q-bus. It used multiplexed data/address lines to save on
signals (38 as against 56 for the Unibus). The processor used a Western Digital
chip set that was microcoded for the PDP-11 base, extended (EIS) and optionally
floating point (FIS) instruction sets. The machine was very close to the
PDP11/40 (without memory management) in its programming, but was much slower
using a 8 bit data path internally to the processor. The original processor
was packaged on a QUAD board with 8Kb of memory, and latter was available
on a dual width board without memory as the LSI-11/2.
This machine replaced the low end PDP11/05 and crammed the CPU onto
one hex board. It has extensive diagnostics in ROM and a console emulator
that used the terminal in a similar way to the LSI series machines. There
was an optional front panel console using 7 segment displays and a key pad.
This machine was meant to replace the PDP11/20, and although much
cheaper, it was substantially slower (even with its faster memory). The
CPU consisted of 2 hex cards which included the console serial interface and
line time clock.
Two different machines had this number. Initially it was a strip
down of the PDP11/20, but this was latter renamed the PDP11/15. The PDP11/10
that most people saw was the same at the PDP11/05, but for OEM users.
A strip down of the PDP11/20, with 2Kb of read-only memory (rope core)
and 256 bytes of read/write memory.
This is the first model of the series, and the only one to be hard
wired instead of using microcode for the instruction decoding. The base
model had 8Kb of
core memory, an ASR-33 teletype (with reader and punch)
and was available in a table top or rack mount box.
The SBC stands for 'Single board computer'. It is a dual width
Q-bus machine using the T-11 processor chip, 16Kb memory, two programmable
serial ports, realtime clock
and 24 bits of I/O (using an Intel 8255 PPI). There were sockets
for additional ROM/EPROM and RAM.
This Q-bus processor was available in several versions, but they
were all based on a new LSI implementation called the F-11 chip set. It
provided the full instruction set of base, EIS and FPU, along with memory
management and ultimately 22 bit addressing for 4Mb of memory. The last
PDP11/23+ was a quad width card with
two serial ports, line time clock and bootstrap/diagnostic ROMS.
This was effectively a Unibus version of the PDP11/23+, with a unibus
map to manage the 22 bit to 18 bit address translation on the Unibus.
This evolved into three versions (/34,/34a,/34c). It was a
a 2 hex board processor, with a optional third quad card to run a
seven segment display and keypad console. A
bit slice floating point processor
was designed using sixteen 2901's, and the CPU was upgraded to the /34a
to show that it was compatible with the FPU. A latter mid-life upgrade was
a cache, which resulted in the /34c. Ironically, the CPU clock was slowed
to accommodate the cache timing.
This was introduced after the successful PDP11/45 as a cheaper
mid-range machine. The CPU had numerous options to allow customers to
choose the performance they required. It has the base instruction set with
EIS and FIS as options (extra microcode and data logic), and a stripped
down memory management without the separate instruction/data space of the
PDP11/45, and the all important MMR1 register was missing. This register
normally provided information about which CPU register had changed by
how much before a memory management abort. Without it, the trap routine
had to calculate how to backup the aborted instruction, and the famous
problem was what to do with "cmp (sp)+,(sp)+".
The last Unibus machines not to use LSI-11 processors (like the
11/84 and 11/94).
It was meant to be a mid range equivalent to the PDP11/70. It fitted
into a single 10 1/2" box, along with a massive power supply that could provide
5 volts at 120 amps. The CPU consisted of 5 hex boards, along with
an optional FPP using sixteen 2901 bit slice processors for a 64 bit data path.
It also had an optional CIS (commercial instruction set).
This was the second of the PDP11 family (after the PDP11/20), and
provided a huge improvement in performance. It used the new Schottky series
TTL to gain speed, and a long microcode word length of 64 bits.
It introduced features that were kept in latter high end machines, such as
the 11/44, 11/70 and J11 chip machines.
These included :-
- Multiply, divide and multiple shift instructions (EIS)
- Optional memory management for 18 bit addressing and 248Kb memory
- Optional floating point processor (FPP)
- Optional fastbus memory for improved speed
- Programmable stack limit register
- Dual register set
This was a
equipped with MOS memory on the fastbus
A Q-bus processor using a 15MHz J11 chip (from the PDP11/73),
but without any cache support.
This was a
with 300ns bipolar memory on the fastbus. For
uncached memory cycles, it was faster than the PDP11/70. There were problems
with the early asynchronous FPP of the 11/45 series, and there was a redesign
of the CPU, backplane and FPP for the latter synchronous unit.
This was meant to be a high end machine, but it lacked separate I/D
space, and only had 18 bit addressing. The FPP instructions were implemented
in microcode, but a hardware FPP was available as an option for accelerated
performance. The machine had an option for a writable control store to
allow new, custom instructions to be programmed.
This was a upgrade of the PDP11/45. It shared a lot of the design
used in the 11/45, but the fastbus was replaced with a 32 bit memory bus,
a 2Kb cache and 22 bit addressing for 4Mb of memory.
The Unibus on this machine was a disaster and had a bandwidth of only 1Mbyte/sec
compared to about 1.7 for other machines. There were extra delays of
100ns for the unibus map and 240ns for the cache cycle.
The first machine to use the new J11 processor chip made by Harris.
This was effectively a PDP11/70 on a chip, including all instructions,
22 bit addressing and an external cache. The early chips ran at 15MHz and
had some buggy microcode, especially for the FPP. Latter chips ran at
An upgrade of the PDP11/73, with a PMI (private memory interconnect)
to speed up memory access time, and the faster 18MHz J11 chip.
It's rumoured that early models ran at 15MHz.
A Unibus version of the PDP11/83, with a Q-bus to Unibus converter
and a unibus map to translate 18 bit to 22 bit addresses.
An upgrade of the /73,/83 machines with no external memory, and
the cache effectively replaced with high speed memory of either 2Mb or 4Mb.
For the first
time, there was a battery backed up time of year clock to retain the
date and time.
This was the fastest of all the PDP11's.
A Unibus version of the PDP11/93 (see PDP11/84).
A strip down of the Professional 350, with less expansion slots and no hard
DEC's failed attempt at a personal computer (along with the Rainbow). It
was based on the F11 chip set (aka PDP11/23), up to 3Mb of addressable memory
and a hacked, menu driven version of RSX-11M called P/OS.
Optional module slots were memory mapped, and the main bus was called CTI
(computer terminal interconnect).
Initial storage options were the RX50 dual 5¼" floppy disk
(not IBM compatible) and the 5Mb RD50 disk (ST506 interface). A monochrome
monitor was standard, with colour as an option.
An updated Professional 350 using the J11 processor chip. It was also used
as the console processor for some of the VAX 8000 series.
These were essentially a VT100 display terminal, with a small quad slot, dual
width cardcage built into the case. Various versions were available with
TU58 tape cartridges or RX01 8" floppies. They normally ran RT-11 software.