Maintenance Control Panel

Overlays, panel with switches and lights, driver card

This panel was originally designed for the PDP11/20 for diagnosing processor faults. Latter processors also had slots for them (PDP11/05, /10, /15, /35, /40, /45, /50, /55 and /70). The floating point processors for the /45, /50, /55 and /70 had separate diagnostic slots. Several peripherals including the RK11 and TM11 also had slots for this device. Each processor or controller had a different overlay for the panel, except the PDP11/20 which had the designations on the PCB etch.

The lights and switches, left to right and top to bottom as they apply to the PDP11/20 are:-

StateDescription
ISR2Condition codes are clocked
TST2Test point on backplane
TST1Test point on backplane
R/W2Clock phase 2
TProcessor Status Bit, trace
TRAPSTrap pending
MSYSNBus master sync
SSYSNBus slave sync
NProcessor Status Bit, negative
ZProcessor Status Bit, zero
VProcessor Status Bit, overflow
CProcessor Status Bit, carry
ISR15Read new PC from vector address
ISR14Read new PS from vector address
ISR12Load new PC
ISR8Load new PS
ISR0Determine interrupt/trap priority
TSR1Collect vector address from bus
ISR3Stack operations for trap for PS
ISR7Stack operations for trap for PC
BSR15Byte swap and writing data
BSR14Byte and word operations determined
BSR12Output transfer from Execute major state
BSR8Wait state for bus transfer
BSR0Output transfer, entered from BSR7
BSR1The instruction major state
BSR3Output of adder paths clocked into BAR
BSR7Address calculation and setting of BAR
SwitchM CLK (manual)
SwitchSSYNC MCLK
SwitchM CLK Enable
SwitchNo Timeout

Abbreviations
BARBus address register
BSRBus shift register
ISRInstruction shift register