This panel was originally designed for the PDP11/20 for diagnosing processor faults. Latter processors also had slots for them (PDP11/05, /10, /15, /35, /40, /45, /50, /55 and /70). The floating point processors for the /45, /50, /55 and /70 had separate diagnostic slots. Several peripherals including the RK11 and TM11 also had slots for this device. Each processor or controller had a different overlay for the panel, except the PDP11/20 which had the designations on the PCB etch.
The lights and switches, left to right and top to bottom as they apply to the PDP11/20 are:-
| State | Description |
|---|---|
| ISR2 | Condition codes are clocked |
| TST2 | Test point on backplane |
| TST1 | Test point on backplane |
| R/W2 | Clock phase 2 |
| T | Processor Status Bit, trace |
| TRAPS | Trap pending |
| MSYSN | Bus master sync |
| SSYSN | Bus slave sync |
| N | Processor Status Bit, negative |
| Z | Processor Status Bit, zero |
| V | Processor Status Bit, overflow |
| C | Processor Status Bit, carry |
| ISR15 | Read new PC from vector address |
| ISR14 | Read new PS from vector address |
| ISR12 | Load new PC |
| ISR8 | Load new PS |
| ISR0 | Determine interrupt/trap priority |
| TSR1 | Collect vector address from bus |
| ISR3 | Stack operations for trap for PS |
| ISR7 | Stack operations for trap for PC |
| BSR15 | Byte swap and writing data |
| BSR14 | Byte and word operations determined |
| BSR12 | Output transfer from Execute major state |
| BSR8 | Wait state for bus transfer |
| BSR0 | Output transfer, entered from BSR7 |
| BSR1 | The instruction major state |
| BSR3 | Output of adder paths clocked into BAR |
| BSR7 | Address calculation and setting of BAR |
| Switch | M CLK (manual) |
| Switch | SSYNC MCLK |
| Switch | M CLK Enable |
| Switch | No Timeout |
| BAR | Bus address register |
| BSR | Bus shift register |
| ISR | Instruction shift register |