Hints on Testing a Dead PDP-11

These notes are the first, very simple, tests to be carried out on a dead PDP-11.

Power Controller

If there is no power getting to the system boxes, then there are several failure modes for the 861 power controller used on many of the older PDP-11's:-

The clips holding the armature on the main power contactor can fracture and not allow the contacts to close.
It's not uncommon for some of the internal wiring to overhead and go open circuit, mainly due to poor crimps on spade connectors generating heat from increasing resistance.
There is an electrolytic capacitor on the power control board that can go open circuit, and make the contactor chatter loudly from being feed unsmoothed DC.
The LC filter or line capacitor can go short circuit and trip the circuit breaker.
The power enable cable from the processor front panel may be disconnected.
The small toggle switch on the controller is normally in the 'remote' position, but you can override the console switch by selecting 'local on'.
If there is a external thermostat (and an internal one) that is faulty, it will activate the 'emergency shutdown', which overrides the 'power on' signal.

Power Supplies and Fans

Check all the supply voltages with both a DVM and oscilloscope on the backplane. The TTL supply should be between 4.9 and 5.1 volts. The other voltages are less critical. It is not sufficient just to use a DVM, since it averages the reading, and the supply may in fact have spikes going to zero volts; also check the ripple and make sure it's less than 200mV on the +5 supply. All PDP-11 models have switch mode power supplies.

If you find low voltages at the backplane, but normal at the regulators, check the connectors, especially the MateLock types used on the modular regulators (type H74X), and the original H720 used on the PDP11/20. On micro PDP-11's (BA-23 box), check the connectors on the wire loom from the supply to the backplane.

On H742 power systems (used on 21" PDP11/35/40/45/50/55/70), the +15 volt regulator is prone to failure, and the -15 will also stop working if it goes. It is a small linear regulator housed in the top of the transformer box. There is a small fan that often fails, and the regulator cooks.

If the power supplies seem OK, check the AC and DC low signals. These are bussed via the Unibus (and Q-Bus), and a failure in any system box can shutdown other parts of the system (depending on the supply design). Again, use an oscilloscope to check for pulses (it should normally be above 2.5 volts) since it may be putting the CPU into power fail mode. All the DC voltages may be OK, but a fault in the AC low logic can still stop the CPU from running.

While you are checking the power supplies, make sure all the fans are running. Some of the newer machines, like the PDP11/44 use special 150Hz, high volume fans, with power derived from the power supply. Machines wired for 230/240 volts may use 115 volts fans wired across the power transformer taps.

The BA11-K mounting box, used as an expansion box or CPU box for some PDP11/34/35, will often fail in the AC/DC low circuit, with the voltages OK but the AC/DC low signals pulsing due to an open circuit ceramic capacitor (I forget which one!)

Simple Memory Test

The next step is some simple memory tests. The first is to check basic memory function, and testing for common core memory failure modes. Starting at 0, deposit 4 consecutive zeros, followed by four 177777, and then another four zeros. Start back at address zero, and read the numbers back and check that they match. There are certain types of core memory faults that will pick up or loose memory bits after reading data.

If you get a struck bit, there is still the possibility that there is a faulty data or address driver on the bus. Try the same test on a different bank of memory, and then an internal CPU register (like the PAR in 11/23/53/44/53/70/73/83/84/93/94). If your memory is interleaved, then errors can happen on every other 16 bit location (address modulus 4).

Simple Processor test

The simplest test is to loop on a single instruction. First, in location zero deposit 5007, which is a 'clr pc' instruction. Start the processor at 0 and it should loop. Next try 777 in any location and it should also loop (it's a 'br .' instruction).

There is a subtle distinction between testing with a 777 (br .) and a 5007 (clr pc) in that the latter is a JAM load of the PC, and the 'br' requires the adder and more of the data paths to be working correctly.

Memory Sizing Program

If the simple tests work, the next step is to find out how much memory is in the system. Without memory management on it will be limited to 56Kb (or 60Kb with memory boards that extend into the I/O page locations). Toggle in the following program :-

	Location	Contents        Opcode          Comment
	
	000004		000006				Bus Error trap
	000006		000000		halt
	000010		000012				Reserved instruction trap
	000012		000000		halt
	000024		000026				Power fail trap
	000026		000000		halt

	001000		012700		mov #770,sp	set the stack
	001002		000770
	001004		005000		clr r0		set memory address
	001006		005720		tst (r0)+	test memory, increment
	001010		000776		br .-2		loop

This program will loop until it generates a bus error trap when it tries to access non-existent memory. Register 0 will contain the top address + 2. On a PDP11/20, the value will be in the data lights. On the older processors, examine memory location 777700; on 11/45/50/50 use the register examine switch; on the LSI based machines, examine $0

Trap Catcher Program

The idea of a trap catcher is to load all the trap vectors so that a random trap can be detected. The first program will trap to 0 on any random trap. Remember on that 11/03 processors (and some other LSI as strap options), that the line time clock is always running unless disabled by the LTC switch on the front panel, and this will cause traps to location 0100.

	Location	Contents        Opcode          Comment

	001000		012706		mov #770,sp	set the stack
	001002		000770
	001004		005000		clr r0		set address pointer
	001006		005020		clr (r0)+	zero memory
	001010		000776		br .-2		loop until halt

This slightly more complicated version will identity the trap location, with the processor halting with the trap location + 6 in the PC register.

	Location	Contents        Opcode          Comment

	001000		012706		mov #770,sp	set the stack pointer
	001002		000770
	001004		005000		clr r0		memory pointer
	001006		012701		mov #2,r1	trap value
	001010		000002
	001012		010120	loop:	mov r1,(r0)+	set trap vector value
	001014		005020		clr (r0)+	set halt instruction in trap
	001016		062701		add #4,r1	update r1 for next trap
	001020		000004
	001022		020600		cmp sp,r0	load up to stack pointer
	001024		001372		bne loop
	001026		000000		halt

After loading memory with the trap catcher, deposit 777 into location 1000 as start (at location 1000). The processor should loop at 1000.

Memory Address Program

The idea of this program is to load every memory location with it's address and then verify. It should normally halt at location 10. If there is an error, the address will be in register 1.

	Location	Contents        Opcode          Comment

	000004	000226				bus error trap
	000006	000000
	000010	000012				reserved instruction trap
	000012	000000

	000200	012706		mov #410,sp	set the stack
	000202	000410
	000204	012700		mov #420,r0	set target memory address
	000206	000420
	000210	010001		mov r0, r1	copy memory address
	000212	010111	loop1:	mov r1, (r1)	write memory
	000214	020111		cmp r1, (r1)	check write
	000216	001401		beq .+2		OK
	000220	000000		halt		initial check error
	000222	005121		com (r1)+	complement the data
	000224	000772		br loop1	loop till bus error
	000226	012737		mov #6,@#4	reload trap vector
	000230	000006
	000232	000004
	000234	010001		mov r0,r1	copy memory address
	000236	005111	loop2:	com (r1)	complement memory
	000240	020111		cmp r1,(r1)	recheck memory
	000242	001401		beq .+2		OK
	000244	000000		halt		memory addressing error
	000246	005721		tst (r1)+	increment memory address
	000250	000772		br loop2

Line Time Clock Interrupt Test

Most of the older PDP11's had a line time clock that would interrupt at mains frequency (50 or 60Hz). On early LSI-11's, it was not programmable but enabled by a switch on the front panel. Load the following program (which is just a trap catcher and interrupt enable), and start. If an early LSI-11's, substitute 000240 for the lines marked #, run the program for a second or two, then enable the clock. The program should halt at address 104 (the interrupt vector address is 100, and the vector is loaded with 102, which then executes a halt at 102, the PC will then be 104).

	Location	Contents        Opcode          Comment

	001000		012706		mov #770,sp	set the stack pointer
	001002		000770
	001004		005000		clr r0		memory pointer
	001006		012701		mov #2,r1	trap value
	001010		000002
	001012		010120	loop:	mov r1,(r0)+	set trap vector value
	001014		005020		clr (r0)+	set halt instruction in trap
	001016		062701		add #4,r1	update r1 for next trap
	001020		000004
	001022		020600		cmp sp,r0	load up to stack pointer
	001024		001372		bne loop
#	001026		012737		mov #100,@#ltc	enable clock interrupt
#	001030		000100
#	001032		177546
	001034		000777		br .		loop for ever

If the processor doesn't halt, then your clock isn't running. If it halts at 6, then the clock register is missing.

Console serial port

Any DL-11 style serial port (including the console) can be simply tested by depositing 060 (octal) into its 'transmitter buffer ', 0777566 in the case of the console. A '0' should appear on the console. If it is anything else, check the baud rate settings.

To check the input register, press the '0', then examine the receive register 0777562 and it should contain 060.

Needles to say, if you are using any of the Qbus processors, or a PDP11/24, /44, /84 or /94 then you need the serial console working to do anything.

As simple serial echo test would be:-

	Location	Contents        Opcode          Comment

	001000		012700		mov #kbs, r0
	001002		177560
	001004		105710	wait:	tstb (r0)	character received?
	001006		100376		bpl wait	no, loop
	001010		016060		mov 2(r0),6(r0) transmit data
	001012		000002
	001014		000006
	001016		000772		br wait		get next character

Note:- PDP11 guru's will notice that I don't test for transmitter ready, as there is little point given that you cannot, type fast enough for it to overrun!

Unexpected HALTS

On the Q-Bus processors, most of the serial controller cards, and the ones intergrated into the CPU card, have a strapping or switch option to halt on break. This can easily be accidentally generated by unplugging or cycling the power on a terminal connected to the console port.

Also, remember that the halt instruction is 000000, so a random jump has a good chance of landing on a memory location containing zeros.

Bus Problems (Unibus)

There are several pitfalls with configuring Unibus systems:-

Make sure that the system has a terminator in the last system unit. Early versions had just resisters, while the latter cards could be either be a terminator/bootstrap, or a terminator with 'bus grant turnaround'.
Check for missing unibus jumpers between system units.
Check that all empty SPC (small peripheral controller) slots have a bus grant continuity card . There are two sorts, a small knuckle busting one that requires adjacent boards to be temporarily remove to install them, and the nice full height card that bridges NPG as well.
The NPG (non-processor request grant) is propagated via wire wraps on the backplane (CA1 and CB1). This wrap is removed if a controller that uses DMA is installed, like a RL11 disk controller. If the board is removed or relocated, the wire wrap must be replaced. If the slot is empty, the new style bus grant continuity card can be installed.

If all the terminations and jumpers look fine, and the power supplies test OK, then you will have to systematically remove bits of the system. The easiest way is to move the bus terminator closer to the processor, step by step.

Bus Problems (Q-Bus)

The Q-Bus is simpler to configure, but there are problems with the range of backplane configurations. Again, there are bus grant signals that are propagated, so there can be problems with empty slots. Check the following :-

On most backplanes, the grant chain zig-zags from left to right, down, then right to left, down, then left to right etc etc. If you have to fit in a quad board, there cannot be any empty slots before it. There are bus grant continuity cards for Q-Bus, but beware, they are different from the Unibus versions.
There are some backplanes that have a 'CD' interconnect to accommodate the RLV11 disk controller card set. All the cards go down the left hand side only. These backplanes were commonly used on PDP-11/23 Plus Systems.
On most of the micro PDP-11 series, the first three slots are 'quad CD' slots with no cards in the right hand side, then the zig-zag system starting at slot 4.
If you have one of the dreaded RQDX1 or RQDX2 MSCP disk controller cards, they must be last card in the system, since they don't propagate some signals properly.
You cannot use a RLV11 disk controller card in a 22 bit backplane without cutting some of the test pin tracks that conflict with the extended address bits.
Some of the older or OEM backplanes don't bus the extended address bits and so won't work as 22 bit backplanes. Also, the run light signal is on different pin in early systems.

Bootstrap problems

Bootstrap failures can result from media errors, incorrect device names or units, or the bootstrap itself may be corrupted. Check the device registers for error bits, or use one of the toggle-in bootstraps and have it halt before executing the loaded bootstrap. For RK05 disks, check this hints section

High speed reader/punch

The high speed reader/punch programming is almost identical to the DL serial and console interfaces. To test the punch, deposit 0377 into the paper punch buffer at 777556. The punch should start and punch one frame of holes. To test the reader, place a tape in it, make sure that the reader switch is in the on position, and deposit 1 into location 777550. The tape should advance by one frame.

As simple tape copy test:-

	Location	Contents        Opcode          Comment

	001000		012700		mov #kbs, r0	I/O registers
	001002		177550
	001004		005210	loop:	inc (r0)	initiate read
	001006		105710	rwait:	tstb (r0)	character received?
	001010		100376		bpl rwait	no, loop
	001012		105760	pwait:	tstb 2(r0)	punch ready ?
	001014		000004
	001016		100376		br pwait
	001020		016060		mov 2(r0),6(r0)	punch frame
	001022		000002
	001024		000006
	001026		000766		br loop		get next frame

Notes:-

This will be rather slow, and is a worst case test for the reader as it will stall betwix frames (it will normally ramp up to 300 characters per second, and the punch can only do 50).
This test will also work on an ASR33 attached to a DL-11 or console

If you are getting read errors, then there are a couple of places to look:-

Clean the photodetector array
The lamp has aged and needs to be replaced (silver deposited inside the envelope).
The threshold needs to be adjusted for the read amplifiers
You have a very early reader that strobes the data off the stepper motor rather than a photodetector under the sprocket hole. You will need to adjust the strobe delay.