Core Memory

Core memory, or more accurately magnetic core memory is a random access memory (RAM) system that was developed at MIT by Jay Forrester in 1951. It was initially very expensive to fabricate but prices dropped as the market developed.

How it Works

The memory consists of an array of ferrite toroids (or cores) that are about 11 mil in diameter. A core is required for each bit of memory and has three wires passing through it, providing the means to select and detect the contents of each bit. (Early core memory used much larger cores, and four wires, X, Y, Sense and Inhibit).

The major property that makes core memory work is the hysteresis of the magnetic material used to make the toroid. Only a magnetic field over a certain intensity (generated by the wires through the core) will cause the core to change its magnetic polarity (or state from '0' to '1'). To select a memory location, one of the X and one of the Y lines are driven with half the current required to cause this change. Only the combined magnetic field generated at the intersection the driven X and Y lines is sufficient to change the state of the bit.

The common sense/inhibit line for each bit, is used to alter or detect the contents of a memory location. Every memory access involves a read/write cycle. A read cycle is always destructive, meaning that the memory contents is lost after the location is read. A read cycle must be followed by a write cycle to restore the contents of the memory location. A read cycle behaves as follows :-

  1. The address of the memory location to be read is decoded into a X and Y coordinate

  2. Only one X and Y line is driven with a pulse of current to access the required location

  3. All other memory locations will at worst, only have half the required magnetic pulse, and will not be affected

  4. If the memory bit accessed in already in the 0 state, the sense/inhibit will not detect a change, and the location will have a value of 0.

  5. If the memory bit accessed was in the 1 state, then the combined pulse of current with flip it into a 0 state, and the sense/inhibit will detect the pulse created by the change, and the location will have a value of 1

A write cycle will always follow a read cycle. Either new data is written, or the old data is put back. Remember that a read cycle destroys the contents of a memory location. A write cycle behaves as follows :-

  1. A read cycle must have preceded the write to set all the bits in the word to 0

  2. The address of the memory location to be written is decoded into a X and Y coordinate

  3. Only one X and Y line is driven with a pulse of current to access the required location. This pulse is in the opposite direction to the read current.

  4. All other memory locations will at worst, only have half the required magnetic pulse, and will not be affected

  5. If the memory location is to contain a 0, the sense/inhibit line is driven with sufficient current to neutralise the effect of the XY lines and the memory location will be unaffected and stay in the 0 state.

  6. If the memory location is to contain a 1, the sense/inhibit line is not driven, and the XY lines will flip the memory core into the 1 state.

Core memory is said to be non-volatile and will not loose it contents when the power is removed. Special logic is included in the memory controller to make sure that it is not possible to alter memory location's content unless the power supply voltages are at their proper levels. This stops random changes to memory contents when power is lost or restored.

Many computer instructions do what is called a read/modify/write cycle. A memory location has its contents read, the computer changes it (perhaps a simple increment in value) and the result written back to the same location. Instead of wasting time by doing a read/write cycle to get the data, and then another read/write cycle to write back the new data, a special access is used. The memory location is read, and then the processor holds the memory controller in a paused state. The new memory data is calculated and then the processor starts the second part of the write cycle to save the new data.

Core memory is also fairly slow, with the early systems having a cycle time of up to 6µs. By the early 1970's, the cycle was down to 1.2µs, and within a few years it halved to 600ns. A technique called interleaving was used to speed up the access time for sequential memory locations. If you have two memory systems that are the same size, then the address decoding can be arranged so that every other memory location goes to a different memory system. This effectively doubles the speed of the memory system when sequential locations are accessed. Some large mainframe computers may have as many as 32 memory banks interleaved to gain speed.

Quirks of Core memory

Core memory, being a magnetic device, is susceptible to the effects of interference. Depending of the geometry of the core layout, certain patterns of memory access can generate sufficient electrical noise for the sense amplifiers to misread the memory data. Several critical adjustments for memory timing, sense levels and drive currents were required. Memory diagnostic programs incorporated a Worst Case Noise test to try an detect this problem.

Another problem that occurred is that the memory X, Y and sense/inhibit wires would start to heat if the same memory location was being accessed at a high rate. When they heat, their resistance would increase, and the driver currents would subsequently drop. This was usually compensated by a temperature detector (usually a thermistor) that adjusted the current to compensate. Again, memory diagnostic programs contained a Core Heating section to detect this problem.