PDP-11 Buses

Unibus

This is original bus for the PDP11/20. The design goal was to use a common (unified) bus for memory and I/O devices. It consisted of 56 bidirectional signals, and allowed a maximum length of 50 ft and 20 loads (or devices) before a repeater was required. (unibus cables, jumpers and terminators) The bus supports asynchronous data transfers so peripherals and memory can respond at different speeds. The original MM11-E memory for PDP11/20s had a cycle time of 1.2us. Later, faster memory could replace it and result in faster program execution. The signals consisted of :-

Signal	Description
A00-A17	Data lines
D00-D15	Data lines
C0, C1	Control lines for transfer type
MSYNC, SSYNC	Data strobing and acknowledge
PA, PB	Device parity (from memory parity controllers)
INTR	Interrupt request
BR4-BR7	Priority bus request lines
BG4-BG7	Bus grant lines
NPR	Non-processor request (DMA)
NPG	Non-processor grant
SSACK	Selection acknowledge (for bus grants)
BBSY	Bus busy for data transfers
INIT	Initialize the bus (power up or reset instruction)
AC LO	AC power has gone (causes power fail interrupt)
DC LO	DC gone (too late!)

Q-bus

This was a cut down (cheaper) version of the Unibus, with 38 signals instead of 56. Sixteen bits of data and address were multiplexed on one set of lines. To save on logic in controllers, there was signal called BBS7, which decoded the I/O register address space. The bus and protocols were extended a couple times (backwards compatible)

The initial 16 bits of address were extended to 18 and finally 22 for 4Mb of memory.
Block mode data transfers were added to allow a single address cycle to be followed by multiple data transfers.
The original single interrupt level was extended to four.

Signal	Description
BDAL00-15	Multiplexed data / address lines
BDAL17-18	Extended address lines and memory error
BAL19-21	Extended address lines
BDOUT	Data output
BDIN	Data input or interrupt
BWTBT	Write byte
BSYNC	Synchronize - address strobe
BRPLY	Reply to BDIN, BDOUT or BIAK
BBS7	Bank select 7 (I/O page)
BIRQ4-7	Interrupt request levels 4-7
BIAKI	Interrupt acknowledge in (daisy chain)
BIAKO	Interrupt acknowledge out (daisy chain)
BDMRL	DMA bus request
BDMGI	DMA acknowledge in (daisy chain)
BDMGO	DMA acknowledge out (daisy chain)
BSACK	DMA acknowledge from device
BINIT	Initialize bus
BHALT	Halt processor
BDCOK	DC power is stable
BPPOK	AC power is normal

Fastbus

This was only available on the PDP11/45/50/55 which had provision for two, dual ported memory controllers. These machines effectively had two unibus data paths that were normally jumpered together. Fastbus memory had a separate, fast interface to the CPU data path and separate port to the unibus for DMA accesses.

Massbus

This was first introduced on the PDP11/70 and latter the VAX 11/780. It was designed as a high speed bus between I/O devices and an interface to the system memory and CPU. Control registers where split between the controller interface and the I/O device. Devices could be mixed on the same cable including disk and tape drives. It was capable of high speed transfer rates and used a 32 bit data path with parity checking of data.

There was a Unibus only controller (RH-11) that sacrificed a lot of the performance (the unibus speed was the problem anyway). For example, the RM03 disk drive (CDC 9762) was for the 11/70 and Vax, and the RM02 was for the unibus machines (11/34-11/60). DEC reduced the rotational speed of the drive from 3600 rpm to 2400 rpm to lower the data transfer rate. This also required different heads, since the 'fly' height was altered by the change in disk speed.