PDP11/70

Operators Console

Switches left to right are :-

Key switch. Power OFF, ON and panel lock (disable halt and start)

Address/data switches, bits 21-0

Lamp test (unlabeled white switch)

Load address. Used for memory examines or deposit. Load start address

Examine memory

Continue from halt

Halt/Enable

Single Instruction / Single Bus cycle

Start

Deposit (lift instead of press)

Sequential examines or deposits would automatically increment the address pointer, while a deposit/examine cycle would leave the address unchanged. With the halt switch down, pressing continue would step the machine a single instruction or bus cycle.

The lights are as follows (left to right, top to bottom) :-

ADRSERR - non-existent memory or access violation
PAR ERR - memory parity error
RUN - program running
PAUSE - CPU inactive waiting for data or halted
MASTER - CPU is the current bus master
USER - CPU in user mode
SUPERVISOR - CPU in supervisor mode
KERNEL - CPU in kernel mode
DATA - last memory reference was to data space
16 BIT - memory mapping mode
18 BIT - memory mapping mode
22 BIT - memory mapping mode
22 bit memory address
Address display mode switch:-
- User D, Supervisor D, Kernel D, Console Physical
- User I, Supervisor I, Kernel I, Program Physical
PARITY HI - high byte parity
PARITY LOW - low byte parity
16 bit data display
Data display mode switch :-
- Data paths, micro address FPU/CPU
- Bus register, display register (programmable)

System Backplane

There are two versions of the processor, the original KB-11B, and the KB-11C which supported the upgraded floating point processor (FP11C). A processor consisted of 22 cards, plus 16 dedicated slots for 4 massbus controllers, DL-11 serial console and 4 small peripheral contoller slots. The system backplane consists of :-

Slot KB11-C KB11-B Card Description

1 CPU and FPU maintenance slots, KW11 line time clock and bus terminator
2 M8126 M8114 FRH floating point fraction data path high order
3 M8127 M8115 FRL floating point fraction data path low order
4 M8128 M8112 FRM floating point ROM and control
5 M8129 M8113 FXP floating point exponent data path
6 M8130 DAP data paths
7 M8131 GRA general registers and ALU control
8 M8132 IRC instruction decode and condition codes
9 M8233 M8133 RAC ROM and ROM control
10 M8134 PDR processor data and unibus registers
11 M8135 TMC trap and miscellaneous control
12 M8136 UBC unibus and console control
13 M8139 TIG timing generator
14 M8137 SAP system address path
15 M8138-YA M8138 SSR system status registers
16 M8140 SCC console cables and system registers
17 M8142 CCB cache control
18 M8143 ADM address memory board
19 >Empty
20 M8144 DTM data memory (cache)
21 M8145 CDP cache data path
22 M8141 MAP unibus map

Slot	KB11-C	KB11-B	Card	Description
1				CPU and FPU maintenance slots, KW11 line time clock and bus terminator
2	M8126	M8114	FRH	floating point fraction data path high order
3	M8127	M8115	FRL	floating point fraction data path low order
4	M8128	M8112	FRM	floating point ROM and control
5	M8129	M8113	FXP	floating point exponent data path
6	M8130		DAP	data paths
7	M8131		GRA	general registers and ALU control
8	M8132		IRC	instruction decode and condition codes
9	M8233	M8133	RAC	ROM and ROM control
10	M8134		PDR	processor data and unibus registers
11	M8135		TMC	trap and miscellaneous control
12	M8136		UBC	unibus and console control
13	M8139		TIG	timing generator
14	M8137		SAP	system address path
15	M8138-YA	M8138	SSR	system status registers
16	M8140		SCC	console cables and system registers
17	M8142		CCB	cache control
18	M8143		ADM	address memory board
19	>Empty
20	M8144		DTM	data memory (cache)
21	M8145		CDP	cache data path
22	M8141		MAP	unibus map