PDP11/45, /50, /55

Operators Console

Switches left to right are :-

Key switch. Power OFF, ON and panel lock (disable halt and start)

Address/data switches, bits 17-0

Lamp test (unlabeled white switch)

Load address. Used for memory examines or deposit. Load start address

Examine memory

Continue from halt

Halt/Enable

Single Instruction / Single Bus cycle

Start

Deposit (lift instead of press)

Sequential examines or deposits would automatically increment the address pointer, while a deposit/examine cycle would leave the address unchanged. With the halt switch down, pressing continue would step the machine a single instruction or bus cycle.

The lights are as follows (left to right, top to bottom) :-

18 bit memory address
Address display mode switch:-
- User I, Supervisor I, Kernel I, Program Physical
- User D, Supervisor D, Kernel D, Console Physical
16 bit data display
Data display mode switch :-
- Data paths, micro address FPU/CPU
- Bus register, display register (programmable)
ADRSERR - non-existent memory or access violation
RUN - program running
PAUSE - CPU inactive waiting for data or halted
MASTER - CPU is the current bus master
USER - CPU in user mode
SUPERVISOR - CPU in supervisor mode
KERNEL - CPU in kernel mode
DATA - last memory reference was to data space

System Backplane

The large backplane to the left is the CPU. The leftmost two thirds is the FPU and CPU with twisted pair wire-wraps. The slots for the early KB11-A processor left to right are:-

CPU and FPU maintenance slots, KW11 line time clock and bus terminator
M8114 FRH - floating point fraction data path high order
M8115 FRL - floating point fraction data path low order
M8112 FRM - floating point ROM and control
M8113 FXP - floating point exponent data path
M8100 DAP - data paths
M8101 GRA - general registers and ALU control
M8102 IRC - instruction decode and condition codes
M8103 RAC - ROM and ROM control
M8104 PDR - processor data and unibus registers
M8105 TMC - trap and miscellaneous control
M8106 UBC - unibus and console control
M8108 SSR - system status registers (KT-11C)
M8107 SAP or M8116 SJB system address path (KT-11C) or system address buffers
M8109 TIG - timing generator

System Boards

Right to left :-

Line time clock (small handle)
Four FPU boards
Ten CPU boards
OEM cache controller on fastbus
DL11 serial console card
OEM disk controller
Two memory cards (128Kb each)

Fastbus Memory Card

This is a fastbus 8Kb MOS memory card. The failure rate for the chips was initially high, and five chips have had to be changed. Early MOS memory did not output TTL voltage levels, and there are a series of level converter chips at the bottom of the card. There is also a controller card required (not shown).

Typical Large System

A typical system would consist of four cabinets containing CPU, expansion for core memory (248Kb), four RK05 disks (2.5Mb each) and a tape drive (TM11+TU10), along with a console terminal (LA36) and line printer (LS-11).

System Components
Component	Weight (lbs)	Power (KW)	Boards
CPU+FPU	450	1.0	15
Memory	350	1.0	32
Disks	560	0.6	24
Tape	500	1.0	-
Console	100	0.2	-
Line Printer	340	0.5	-
Totals	2300	4.3	71

In total, the four cabinets would be eight feet wide and six feet high. In addition to the 5.3Kw of power for the system, an additional 3KW of air conditioning would probably be required.

Processor documentation

Processor Maintenance Manual (link)

Processor block diagrams and microcode flow charts. The tiff files are slightly smaller.

Processor block diagram page 1 of 3 as gif or tiff
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Microcode flow diagram page 1 of 14 as gif or tiff
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