Switches left to right are :-

• Key switch. Power OFF, ON and panel lock (disable halt and start)
• Address/data switches, bits 17-0
• Load address. Used for memory examines or deposit. Load start address
• Examine memory
• Continue from halt
• Halt/Enable
• Single Instruction / Single Bus cycle
• Start
• Deposit (lift instead of press)

Sequential examines or deposits would automatically increment the address pointer, while a deposit/examine cycle would leave the address unchanged. With the halt switch down, pressing continue would step the machine a single instruction or bus cycle.

The lights are as follows (left to right, top to bottom) :-

• 18 bit memory address
• RUN - processor running
• BUS - bus busy
• FETCH - instruction fetch bus cycle
• EXEC - instruction execute phase
• 16 bit data display
• SOURCE - processor accessing source data
• DESTINATION - processor obtaining destination data
• ADDRESS - source or destination address cycle

When the processor halts, the address display will contain the halt address plus two. The data display will contain the last data transfer. If this was move to a register, the contents are displayed. This can be used to show error codes on halts.