PDP11/20 Console

Switches left to right are :-

Sequential examines or deposits would automatically increment the address pointer, while a deposit/examine cycle would leave the address unchanged. With the halt switch down, pressing continue would step the machine a single instruction or bus cycle.

The lights are as follows (left to right, top to bottom) :-

When the processor halts, the address display will contain the halt address plus two. The data display will contain the last data transfer. If this was move to a register, the contents are displayed. This can be used to show error codes on halts.