Operators Console

* Note that latter modes had a pdp11/20 logo on the front panel

Switches left to right are :-

Sequential examines or deposits would automatically increment the address pointer, while a deposit/examine cycle would leave the address unchanged. With the halt switch down, pressing continue would step the machine a single instruction or bus cycle.

The lights are as follows (left to right, top to bottom) :-

  • 18 bit memory address
  • RUN - processor running
  • BUS - bus busy
  • FETCH - instruction fetch bus cycle
  • EXEC - instruction execute phase
  • 16 bit data display
  • SOURCE - processor accessing source data
  • DESTINATION - processor obtaining destination data
  • ADDRESS - source or destination address cycle

When the processor halts, the address display will contain the halt address plus two. The data display will contain the last data transfer. If this was move to a register, the contents are displayed. This can be used to show error codes on halts.

System Backplane

The system box is made up of a power supply (black box on the left), and 'system units' which are the rectangular blocks with the wire-wrap connections. Each 'system unit' had four slots, each with 6 rows. Rows A and B were for unibus connects and power, and except for the first four CPU positions never had cards in them, since the fan bay covered the top of them (front of photo). The CPU used the first three backplanes (right to left), followed by a memory unit (8Kb), and in this example, the last backplane was a RK11 disk controller. There is an empty position for another backplane, the H720 power supply (in this case, a latter model H720-F) and the unibus cable can be seen exiting on the left hand side (flat white cable).

System Boards

One of the 15 cpu boards (not all this size). Notice the low density and hand laid PCB design. The CPU used standard TTL, HTTL and Signetic 8000 series logic.

Other Images