Switches left to right are :-
Sequential examines or deposits would automatically increment the address pointer, while a deposit/examine cycle would leave the address unchanged. With the halt switch down, pressing continue would step the machine a single instruction. The 'PANEL LOCK' disables the start and halt switches.
The lights are as follows (left to right) :-
The 16 bit display is multiplexed to show either data or memory address. When the processor halts, the display will contain the halt address plus two. When the 'examine' or 'deposit' switch is depressed, the display will show the memory location to be used, and when the key is released, the data is displayed.
The PDP11/05/10 could execute a program out of the registers at memory
locations 0177700-0177706. The program counter
would only increment by one instead of two, and odd PC values were allowed.
Branch instructions still went two locations per offset count.
Very handy to scope out memory faults.
Location Data Instruction Comments
0177700 0057153 tst (r3) ; read location pointed to by r5
0177701 000240 nop ; do nothing, needed because of branch
0177702 000777 br .-2 ; goes to 177700
0177703 xxxxxx ; address of test location
Start execution at 0177700 and check out the faulty memory with a CRO.